VDTT+IEC = VLSI of IIT-D
This is the interview experience of my friend Himanshu Lohani, who secured AIR 88 with a Gate score of 879 in GATE 2016 ECE at IIT Delhi conducted on May 17 & 18.
VDTT is a completely sponsored
course. It comprises of three stream CSE +EE +EC. There is no reservation in
this, only course in Delhi without reservation with intake of around10 students.
Some employees are sponsored by their companies and gate freshers qualified are
to be sponsored from industries Texas, Cadence, Cypress and internal project.
Gate cutoff score for both course
was 800. As my gate score is 879, AIR-88. I was shortlisted for both.
VDTT 1st Round
I didn’t crack first round which is professor round. Here I am
giving my experience. There were total 91 candidates called for VDTT I had seen
the list during document verification, out 10 were from CSE, 61 from EC and 20
from EE. Many candidates were absent that day. There were total 5 to 6 panels,
3 are for EC and for rest 1 each.
The Asst. Professor asked me about college and title of my
project. I have my B.Tech Thesis and one publication in Elsevier journal. I
thought of showing him, but he straightly declined offer: p, busy on his work
in laptop also. I was comfortable in CMOS, my project was based on that "Design,
implementation and comparison of multiplier topologies using 90nm
technology".
1. The first question was based on CMOS inverter to
determine current supplied from supply to ground. The input voltage waveform
was practical step waveform. I thought of drawing output voltage, so I draw
that. He said wrong. Think again. Then I saw carefully and the curve was Id Vs time.
So I tried using current equation of saturation and said parabolic shape up to
some region. Now some short of argue there. I said its parabolic shape. And he
was not agreeing he said not parabolic, it is squared law. I thought what he is
saying Id=K (Vgs-Vt) ^2 is parabolic between Id and Vgs.
I make incorrect wave. I knew the concept to see which will be on and the.
Check, but at that time wasn’t getting. So after that he explained and after
some words I get and I extended further. He straightly said u didn’t know the
basic question how u will do other. "Kya kiya jaye ab". He asked are u
comfortable with analog. Now in analog I don’t have such grip so I said I am
comfortable in this Domino cmos, and others
2. Second question was to make Boolean Expression using mos.
Now he was saying complementary structure draw. I thought of that as CPL
(complementary pass transistor) and draw that. He didn’t get what I make. Then
I said, I knew Domino Cmos also. I drew that also for that expression and was
explaining the operation precharge and evaluate etc. Charge sharing concept.
He was not satisfied again. After discussion a bit more, I got he was asking
for basic CMOS ckt pmos and nmos one. Oh god it takes so much time to
understand what he actually wants!.
3. He asked what type of interconnects wire we use while
fabrication. Thick, thin and mix of both. I said thick because Resistance will
be less.
4. Id Vs Vds plot he asked. Then after that he asked what
this slope indicates. That was lambda, channel length modulation parameter. How
to resolve it.some question I don’t recall now
Overall Interview was not good, and I didn’t clear Vdtt first
round.
IEC INTERVIEW EXPERIENCE
The next day was interview of Electrical dept. One has to give
only two interviews based on his interests and the shortlisting criteria. 1st preference
on first day and 2nd on next day. I only went for IEC.
We all were asked to sit inside lab. There was 112 or 120 general
candidates shortlisted. Separate lists are for general, obc, SC etc. After document
verification we have to fill a form mentioning area of interest, gate score. I write
Digital CMOS". There were total 7, 8 professors in pair seated together and
one to one interview was going on. Before interview I heard a lot about this that
if someone has high gate score he will be selected even his interview was worst.
But this was not, there were candidates under 30, 50 rank also with gate score
920+ but they weren’t selected. Although the final selection is Gate score+ Interview.
So interview matter a lot.
The professor started by college name and area of interest. He
started by saying FSM, state design can I ask. I was not so much comfortable in
FSM, so I hesitated and said for MOS and digital CMOS. My interview was more of
a discussion, he asked questions from;
- Pass transistor and its disadvantage.
I explained him about threshold voltage drop in nmos pass Tx. He said ok this
can be one, tell other. he want to listen particular term which I said after
sometime.
- About TG transmission gate
and why we don’t use for designing.
- Some question on counters,
dynamic pass Tx.
The main question which takes much time was designing question.
he said ok now I am giving u question in FSM. I can’t reject second time. I agreed
and the question was to design FSM design for the logic which moves only in two
states 39sec and 255sec using mod-64 with clock 1sec. literally that time I was
clueless no idea what he asked. I tried by thinking counter 6 bit. and he agreed
yes right u can use this. So it all went through discussion. He was also solving
and I too. Lot of time goes in this. 35-40 min in designing ques. he come with a
soln and I again said and sir there will be this problem, then again he think. And
I was expert in discussion in my college viva too, that helped me.
In between Associate professor adjacent to him was discussing
to student about what we should do in life, about drdo, isro barc, startups etc
.I was so much in interest that my teacher interrupt me and said to focus in the
question. I was sitting so long that 4 candidates come and go to adjacent seat interviewed
by other teacher. In between they start their lunch eating pizzas, gathering of
all professors. At last, I showed him my publication and about some work done.
Overall the experience was good and it took 1 hour plus and that
FSM question till end I didn’t get how he was solving. I felt positive about the
result and after result came yes my name was in the list :).There were tot 16 general
candidates selected out of 112 (obviously some are absent). 5 for MS and 11 for
M.tech.
Thank you himanshu for sharing your interview experience,hope it helps many to get past interviews at IIT-D in upcoming years.